1. Field of the Invention
The present invention relates to a field effect transistor, and more particularly to a heterostructure insulated-gate field effect transistor.
2. Description of the Related Art
There has been increasing in recent years a demand for field effect transistors of high performances. In order to improve the performance of a field effect transistor, it is generally required that a channel layer of a field effect transistor be thinner and have a higher carrier concentration. However, in the case where a channel layer is made thinner with a higher carrier concentration in a conventional field effect transistor having a structure in which a channel layer is disposed immediately under a gate electrode, the gate breakdown voltage becomes lower due to the higher carrier concentration, thereby restricting an improvement in the performance of the transistor.
In order to overcome the above drawback, a heterostructure insulated-gate field effect transistor 1 (HIGFET) shown in FIG. 7 has been proposed. The field effect transistor 1 has a stacked structure formed by an epitaxial growing method. More specifically, in the field effect transistor 1, a high-resistance semiconductor buffer layer 3 is formed on a GaAs semi-insulating substrate 2. An n-GaAs low-resistance channel layer 4 is formed on the buffer layer 3, and a high-resistance barrier layer 5 made from and undoped high-bandgap material, for example, i-AlGaAs, is disposed on the channel layer 4. Moreover, an n-GaAs low-resistance contact layer 6 is formed on the barrier layer 5.
A source electrode 7 and a drain electrode 8, both of which are formed of ohmic electrodes, are disposed on the surface of the contact layer 6, thereby forming a source region and a drain region, respectively. Moreover, the contact layer 6 is partially removed to expose the barrier layer 5. A gate electrode 9 made of a Schottky electrode is disposed on the surface of the barrier layer 5, thereby forming a gate region.
According to the structure, the barrier layer 5 is disposed on the channel layer 4. Thus, the channel layer 4 can further be made thinner with high carrier concentration without seriously impairing a reduction in the gate breakdown voltage, which has been discussed above, thereby enhancing the performance of the field effect transistor 1.
In the field effect transistor 1 shown in FIG. 7, however, the barrier layer 5, which is made from a high-resistance and high-bandgap material, is provided between the contact layer 6 and the channel layer 4. This disadvantageously increases the access resistance from each of the source and drain regions to the channel layer 4 (the series resistance between the source/gate or the drain/gate).
As the method for overcoming the above drawbacks, the following methods for reducing the series resistance components of the source and drain regions have been proposed: (1) the method for selectively implanting ions into the source and drain electrodes (DMT: Doped channel hetero Mis-FET); and (2) the method for regrowing a low-resistance crystal in the source and drain regions (DC-HIGFET: Doped Channel Heterostructure Insulated-Gate FET).
FIG. 8 illustrates an insulated-gate field effect transistor 10 obtained by using the above selective ion-implanting method (1). A low-resistance Si-doped ion-implanted layer 11 is formed in each of the source region and the drain region. Although the series resistance components of the source and drain region can be reduced in the insulated-gate field effect transistor 10, the selective ion-implanting method shown in FIG. 8 requires complicated and time-consuming process steps, such as ion implantation, the formation of a protective film (plasma process at approximately 300.degree. C.), heat treatment (approximately 800.degree. C.) for activating the implanted ions, and the removal of the protective film, after completing the epitaxially growing step. This increases the manufacturing cost and also deteriorates the characteristics of the field effect transistor 10, such as reproducibility and uniformity.
Moreover, during the high-temperature heat treatment process step, the impurity distribution which is precontrolled by the epitaxial growing may be disordered. Additionally, since the plasma process is performed to form the protective film, the GaAs substrate 2 and the semiconductor layers 3 through 5 may be seriously damaged.
FIG. 9 shows an insulated-gate field effect transistor 12 obtained by using the above selective regrowing method (2). A low-resistance n-GaAs regrown layer 13 obtained by regrowing a low-resistance crystal region is disposed in each of the source region and the drain region.
The selective regrowing method illustrated in FIG. 9 also requires a complicated process. More specifically, after the semiconductor layers 3 through 5 are epitaxially grown on the GaAs substrate 2, a pattern of, for example, a protective film, is made. Then, portions of the semiconductor layers 3 through 5 are etched by using the protective film as a mask, and the n-GaAs regrown layer 13 is epitaxially grown. Accordingly, in this regrowing method, as well as in the foregoing ion implanting method, the process is complicated and time-consuming. This increases the manufacturing cost and also deteriorates the characteristics of the field effect transistor 12, such as reproducibility and uniformity.
Further, in the selective regrowing method, growing selectivity requires a protective film pattern, and a large amount of impurity remains on the regrowing interface, which adversely influences the reliability and characteristics of the field effect transistor 12.
As is seen from the foregoing description, the field effect transistors 10 and 12 having the structures shown in FIGS. 8 and 9, respectively, present the problems of a complicated manufacturing process, poor reproducibility and reliability, which further deteriorates the characteristics of the transistor. Both the field effect transistors 10 and 12 also need the patterning spaces between the gate electrode and the source or drain electrode so as to allow a photolithographic process to be performed. This means that a longer distance between the gate electrode and the source or drain electrode is required, which results in an increase of series resistance adversely. That is, the series resistance cannot be reduced in spite of requiring a complicated process.
For the reasons explained above, a heterostructure insulated-gate field effect transistor having an excellent performance has not been realized commercially, and there is a need for a field effect transistor which has a low series resistance and can be produced by a simple production process.